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| 1.5 - 2.5 GHz LNA Switch PA Technical Data HPMX-3003 Features * GaAs MMIC LNA-SwitchPower Amp for 1.5 - 2.5 GHz Transceiver Use * LNA: 2.2 dB NF, 13 dB Ga @ 1.9 GHz * Switch: 55 dBm OIP @ 1.9 GHz * Power Amp: +4 dBm in, +27.5 dBm out, 23.5 dB Gain, 35% add @ 1.9 GHz * 3 or 5 V Operation * JEDEC Standard SSOP-28 Surface Mount Package Plastic SSOP-28 H 30PMX YY 03 WW Description Hewlett-Packard's HPMX-3003 combines a Low Noise Amplifier, GaAs MMIC switch, and 27.5 dBm power amp in a single miniature 28 lead surface mount plastic package. This RFIC would typically serve as the "front end" and power stage of a battery operated wireless transceiver for PCS or ISM band use. Each section of the RFIC can also be used independently. 15 Antenna C1 14 Package Pin Configuration 25 PA out 24 Gnd 22 PA out 21 PA out 18 SW2 27 VG2 26 Gnd 23 Gnd 20 Gnd 19 Gnd 17 Gnd 16 C2 28 Gn Applications * Personal Communications Systems (PCS) * Cordless Telephone Systems * 2400 MHz Wireless LANs and ISM Band Spread Spectrum Applications VD1 7 LNA out 8 Gnd 1 Gnd 2 Gnd 3 PA in 4 Gnd 5 Gnd 6 HPMX 3003 YYWW Gnd 9 Gnd 10 LNA in 11 Gnd 12 SW1 13 The single-supply LNA makes use of the low noise characteristics of GaAs to create a matched, broadband amplifier with target performance of 13 dB gain and 2.2 dB noise figure. The switch provides +55 dBm IP3 for linear operation. The power amplifier produces up to 820 mW with 35% power added efficiency. The HPMX-3003 is fabricated with Hewlett-Packard's GaAs MMIC process, and features a nominal 0.5 micron recessed Schottkybarrier-gate, gold metallization, and silicon nitride passivation to produce MMICs with superior performance, uniformity and reliability. Functional Block Diagram LNA out C1 Antenna C2 PA in (VG1) SW2 PA out VD1 VG2 VD2 LNA in SW1 5965-1403E 7-82 HPMX-3003 Absolute Maximum Ratings[1] Symbol Pdiss Pin Vd Vcont Tch TSTG Parameter Power Dissipation[2,3] CW RF Input Power Device Voltage Control Voltage Channel Temperature Storage Temperature Units mW dBm V V C C Absolute Maximum[1] LNA 250[2,3] +20 8 -- 175 -65 to 150 Absolute Maximum[1] Switch +33 -- -6 175 -65 to 150 Absolute Maximum[1] Power Amp 1500[2,3] +20 8 -- 175 -65 to 150 Notes: 1. Operation of this device above any of these limits may cause permanent damage. 2. Tcase = 25C 3. Derate at 18.2 mW/C for TC > 78C Thermal Resistance [2]: jc = 55C/W Recommended operating range of Vcc = 2.7 to 5.5 V, Ta = -40 to + 85 C HPMX-3003 Standard Test Conditions Unless otherwise stated, all test data was taken on packaged parts under the following conditions: Ta= 25 C, Zo = 50 Vcc = +3.0 V DC, Vcontrol = -3.0 V DC, VD1 = +3.6 V DC LNA Pin = -20 dBm, PA Pin = +4 dBm, frequency = 1.9 GHz Perfomance cited is performance in test circuit shown in Figure 17. HPMX-3003 Guaranteed Electrical Specifications Standard test conditions apply unless otherwise noted. Symbol Gtest Pout I d LNA Parameters and Test Conditions LNA gain through switch Output power through switch LNA bias current Units dB dBm mA Min. 9.0 24.0 Typ. 11 25.5 6.5 Max. 9.5 7-83 HPMX-3003 Summary Characterization Information Standard test conditions apply unless otherwise noted. All information tested in 1900 MHz Test Circuit, and reflects performance of test circuit at 1900 MHz. Symbol LNA NF |S21|2 IRL ORL IIP3 Switch P1dB Parameters and Test Conditions Noise Figure 50 Gain Input Return Loss Output Return Loss Input Third Order Intercept Units dB dB dB dBm dBm dBm dBm dB dB dB dB dB % dBm mA Typ 2.2 13 15 12 -1 +23 +29 +55 0.8 15 26 0.5 23.5 35 +27.5 450 Output Power C1 to C2 = 3 V where insertion loss is increased by 1 dB P1dB Output Power C1 to C2 = 5 V where insertion loss is increased by 1 dB[1] IP3 Third Order Intercept S21 on Insertion Loss, on channel S21 off Isolation, off channel IRLon Return Loss, on channel IRLoff Return Loss, off channel Power amp (Vg = -.8 V required) GP Gain VD1 = 3.6 V, Pin = +4 dBm PAadd Power Added Efficiency VD1 = 3.6 V Pout Id PA Output Power Transmit Current VD1 = 3.6 V, Pin = +4 dBm VD1 = 3.6 V, Pin = +4 dBm Note: 1. The P 1dB of the switch can be improved by increasing the difference between the values of C1 and C2 from the normal 3 V (+23 dB P1dB) to 5 V (+29 dB P1dB). HPMX-3003 Pin Description Gnd 1 Gnd 2 Gnd 3 PA in 4 Gnd 5 Gnd 6 VD1 7 LNA out 8 Gnd 9 Gnd 10 LNA in 11 Gnd 12 SW1 13 C1 14 28 Gn 27 VG2 26 Gnd 25 PA out 24 Gnd 23 Gnd 22 PA out 21 PA out 20 Gnd 19 Gnd 18 SW2 17 Gnd 16 C2 15 Antenna Figure 1. HPMX-3003 Pin Outs and Schematic. 7-84 HPMX-3003 Pin Description Table No. Mnemonic Description 1 2 3 4 Gnd Gnd Gnd PA in ground ground ground input to Power Amplifier ground ground Drain bias of PA stage 1 output of LNA Typical Signal 0V 0V 0V DC: -0.75 V RF: +4 dBm 0V 0V +3 V, 100 mA DC: +3 V, 5 mA RF: -7 dBm Description Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. Bias through 500 resistor and 100 pF capacitor. 50 transmission line with DC blocking capacitor (>24 pF) to input. Shunt 2.7 pF used on test board to match input at 1.9 GHz. Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. Set drain bias to 3 V (can be tied to same rail as PA out). Bypass with 100 pF capacitor at pin. Bias through 5 nH choke (printed on PC board) and 100 pF bypass capacitor to 10 resistor and 1000 pF bypass capacitor. Can be operated from 3 to 5 V supply line. 50 transmission line with DC block (>24 pF) to receiver. Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. 50 transmission line from switch. Input blocking capacitor (24 pF) and shunt 5 nH inductor to ground (noise match at 1.9 GHz) required. Typically a filter is employed between the LNA input and the switch. Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. Switch input or output. Symmetrical with SW2. 50 transmission line to LNA (or PA). Line should not carry DC voltage. High impedance line to control switch, used in conjunction with C2. C2 should be open when C1 is closed. 50 transmisson line to/from antenna. Line should not carry DC voltage. High impedance line to control switch, used in conjunction with C1. C1 should be open when C2 is closed. Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. Switch input or output. Symmetrical with SW1. 50 transmission line to PA (or LNA). Line should not carry DC voltage. Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. 2.7 pF chip capacitor to ground provides 1.9 GHz output match for PA. 50 transmission line to switch. LC choke and blocking C used. Typically a filter is employed between the PA output and the switch input. Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. Leave unconnected; use pins 21 & 22 for PA out. Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. Provide bias through 10 resistor. Bypass to ground at pin with 10 pF capacitor, and on power supply side of resistor with 1000 pF capacitor. Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. 5 6 7 8 Gnd Gnd VD1 LNA out 9 10 11 Gnd Gnd LNA in ground ground input of LNA 0V 0V DC: 0 V RF: -20 dBm 12 13 Gnd SW1 ground switch terminal 1 switch control 1 switch center pole switch control 2 ground switch terminal 2 ground ground output of PA output of PA 0V DC: 0 V RF: -20 dBm closed: 0 V open: -3 to -5 V DC: 0 V RF: +26 dBm closed: 0 V open: -3 to -5 V 0V DC: 0 V RF: +4 dBm 0V 0V DC: 3 V, 350 mA RF: +27 dBm 14 15 16 17 18 C1 Antenna C2 Gnd SW2 19 20 21 22 Gnd Gnd PA out PA out 23 24 25 26 27 Gnd Gnd PA out Gnd VG2 ground ground output of PA ground Gate bias on PA stage 2 ground 0V 0V DC: 3 V, 350 mA RF: +27 dBm 0V -0.75 V 28 Gnd 0V 7-85 HPMX-3003 Typical Performance Standard test conditions apply unless otherwise noted. 2.4 GHz performance is performance in test circuit shown in Figure 18. Some aspects of performance are determined by the test circuit impedances. 10 9 8 20 5 CURRENT (mA) 7 6 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 6 GAIN (dB) 1900 MHz 10 NOISE FIGURE (dB) 15 2400 MHz 4 3 2400 MHz 2 1900 MHz 5 1 0 2.5 3 3.5 4 4.5 5 5.5 6 0 2.5 3 3.5 4 4.5 5 5.5 6 VOLTAGE (V) VOLTAGE (V) VOLTAGE (V) Figure 2. LNA Current vs. Device Voltage at 1900 MHz. Figure 3. LNA Gain vs. Device Voltage and Frequency. Figure 4. LNA Noise Figure vs. Device Voltage and Frequency. 8 7 20 5 4 GAIN (dB) 5 4 3 2 1 0 -60 -40 -20 0 20 40 60 80 100 NOISE FIGURE (dB) 0 20 40 60 80 100 6 15 CURRENT (mA) 3 10 2 5 1 0 -60 -40 -20 0 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) TEMPERATURE (C) TEMPERATURE (C) Figure 5. LNA Current vs. Temperature at 1900 MHz. Figure 6. LNA Gain vs. Temperature at 1900 MHz. Figure 7. LNA Noise Figure vs. Temperature at 1900 MHz. 12 35 1900 MHz 30 50 10 Stg 2 40 25 CURRENT (mA) 20 15 10 6 PAE (%) 8 Pout (dBm) 2400 MHz 30 1900 MHz 20 2400 MHz 10 4 Stg 1 2 2.5 5 0 2.5 3 3.5 4 4.5 5 5.5 6 3 3.5 4 4.5 5 5.5 6 0 2.5 3 3.5 4 4.5 5 5.5 6 VOLTAGE (V) VOLTAGE (V) VOLTAGE (V) Figure 8. PA Current vs. Device Voltage at 1900 MHz. Figure 9. PA Output Power vs. Supply Voltage and Frequency. Figure 10. PA Power Added Efficiency vs. Supply Voltage and Frequency. 7-86 HPMX-3003 Typical Performance, continued Standard test conditions apply unless otherwise noted. 2.4 GHz performance is performance in test circuit shown in Figure 18. Some aspects of performance are determined by the test circuit impedances. 400 350 CURRENT (mA) 300 250 200 150 100 Stg 1 50 -60 -40 -20 0 20 40 60 80 100 0 -60 -40 -20 0 20 40 60 80 100 0 -60 -40 -20 0 20 40 60 80 100 Stg 2 POWER (dBm) 35 30 40 25 20 15 10 10 5 PAE (%) 30 50 20 TEMPERATURE (C) TEMPERATURE (C) TEMPERATURE (C) Figure 11. PA Current vs. Temperature at 1900 MHz and VD1 = 3.6 V. Figure 12. PA Output Power vs. Temperature at 1900 MHz and VD1 = 3.6V. Figure 13. PA Power Added Efficiency vs. Temperature at 1900 MHz and VD1 = 3.6V. 0 0 0 ISOLATION/R.L. (dB) -1 -10 R.L. (dB) I.L. (dB) 1.6 1.8 2.0 2.2 2.4 2.6 -2 -1 -2 -20 -3 -3 -30 -4 -4 -40 1.4 1.6 1.8 2.0 2.2 2.4 2.6 -5 1.4 -5 1.4 1.6 1.8 2.0 2.2 2.4 2.6 FREQUENCY (GHz) FREQUENCY (GHZ) FREQUENCY (GHZ) Figure 14. Switch Isolation and "ON" State Return Loss vs. Frequency. Figure 15. Switch "OFF" State Return Loss vs. Frequency. Figure 16. Switch "ON" State Insertion Loss vs. Frequency. HPMX-3003 Typical Scattering Parameters for the LNA, Common Source, ZO = 50 , VD = 3 V, ID = 5 mA Frequency GHz Mag S11 Ang Mag S21 Ang Mag S12 Ang Mag S22 Ang 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 0.97 0.96 0.95 0.94 0.92 0.90 0.88 0.85 0.82 0.78 0.75 -27 -33 -40 -47 -54 -62 -70 -79 -89 -99 -110 2.00 2.06 2.13 2.20 2.28 2.36 2.45 2.54 2.63 2.71 2.79 158 150 142 134 125 117 109 100 90 81 71 0.035 0.036 0.037 0.038 0.038 0.039 0.039 0.040 0.042 0.045 0.050 -12 -17 -23 -30 -39 -49 -62 -77 -95 -115 -135 0.91 0.91 0.90 0.88 0.87 0.86 0.84 0.83 0.81 0.79 0.78 -22 -27 -31 -36 -41 -46 -50 -55 -60 -65 -71 7-87 30 pF PA in 100 pF 2.7 pF 10 VG2 ~ - 0.75V 10 pF 30 pF VG1 ~ - 0.75V 500 VD1 = 3.6V 100 pF 30 pF LNA out 3.0V 1000 pF LNA in 5 nH SW1 C1 C2 Antenna 10 5 nH SW2 30 pF 2.7 pF 18 nH PA out VD2 = 3.6V 1000 pF 100 pF Figure 17. HPMX-3003 Test Circuit (1900 MHz). 30 pF PA in 100 pF 1.5 pF 10 VG2 ~ - 0.75V 10 pF 30 pF VG1 ~ - 0.75V 500 VD1 = 3.6V 100 pF 30 pF LNA out 3.0V 1000 pF LNA in 2.5 nH SW1 C1 C2 Antenna 10 2.5 nH SW2 30 pF 1.5 pF 18 nH PA out VD2 = 3.6V 1000 pF 100 pF Figure 18. HPMX-3003 Test Circuit (2400 MHz). 7-88 JEDEC Standard SSOP-28 Package Outline Drawing 8.255 (0.325) 6.000 (0.236) 3.850 (0.152) TYPICAL DIMENSIONS ARE IN MILLIMETERS (INCHES) MEETS JEDEC OUTLINE DIMENSIONS 10.000 (0.394) 1.400 (0.055) 0.635 (0.025) 0.185 (0.007) 0.250 (0.010) 0.600 (0.024) Part Number Ordering Information Part Number HPMX-3003-TR1 HPMX-3003-BLK No. of Devices 1000 25 Container Tape and Reel Tape 7-89 |
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